The present invention relates to a memory cell that is a constituent element of a semiconductor memory cell array, and more specifically to a structure thereof.
There is little room for further improvements in packing density, capacity and power dissipation of semiconductor memory cell arrays by scaling down the dimensions of memory cells of conventional structures. To overcome this, the advent of memory cells having novel structures and operating principles has been expected. One of such memory cells is a quantum dot memory cell.
FIG. 1 shows the structure of a quantum dot memory cells (K. Yano et al., IEEE Trans. Electron Devices, 41, 1628, 1994). When a negative bias is applied to a polysilicon thin film, electrons are transferred from the gate to the domain and stored in the domain. Thus, the domain becomes negatively charged. The resulting Coulomb's repulsive force narrows the current channel in the polysilicon, thereby reducing the conductance of the channel.
The stored electrons are returned from the domain to the gate by applying a positive bias to the polysilicon thin film. Thus, the current channel is restored to its original conductance. Sensing changes in the conductance of the current channel allows discrimination between "0" and "1" states of the cell.
On the left-hand side of FIG. 1 are shown applied voltages for placing the memory cell (1) in the "1" state and the memory cell (2) in the "0" state with the word line (WL1) selected. On the right-hand side of FIG. 1 are shown readout currents from two cells that share a word line.
FIG. 2 shows the structure of a memory cell fabricated by Tiwari et al. in IBM (S. Tiwari et al., Appl. Phys. Lett., 68, 1377, 1996). This cell is characterized in that silicon microcrystals, called nano-crystals, are buried in the gate oxide of a general MOS transistor.
When a high potential is applied to the gate, electrons are transferred from the channel formed below the silicon-silicon oxide interface to the silicon microcrystals through the tunnel oxide and stored in the microcrystals.
When electrons are stored in the silicon microcrystals, the threshold of the MOS transistor shifts, allowing discrimination between the two states of the cell.
In the cell structure of FIG. 1, electrons are stored in the grains of the polysilicon thin film. However, difficulties are involved in making the grains uniform in size. In addition, it is difficult to control the position of the grains. Poor precision in the size and position of the grains will make readout current vary widely from memory cell to memory cell. As a result, readout errors become easy to occur. This problem will be solved by providing multiple grains for one cell and combining currents from the grains into one readout current to thereby checking variations in readout current. However, this method will increase the area of a memory cell, failing to meet high packing density and low power dissipation requirements of semiconductor memory arrays.
In the technique of FIG. 2, the narrowing of the channel based on the Coulomb's repulsive force and hence a reduction in channel conduction cannot be expected much because the channel is relatively wide. In addition, the silicon micro-crystals are not controlled with respect to their arrangement and are distributed randomly over the channel. Thus, scaling down of the dimensions of the cell will make the characteristics vary widely from cell to cell. For this reason, difficulties are involved in increasing the packing density and reducing the power dissipation.